Fast read port for register file

ABSTRACT

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of pending U.S. patent application Ser. No.11/130,929; filed May 17, 2005.

TECHNICAL FIELD

The invention relates to memory systems and read operations. Morespecifically, the invention is a single-ended read port and senseamplifier with integral precharge capability.

BACKGROUND ART

A static memory cell constructed from six transistors is commonlyapplied in memory designs to fulfill requirements for short access cycletimes, high-frequency data rates, low power consumption, and excellentimmunity from extreme environmental conditions.

With reference to FIG. 1A a six transistor (6-T) cell latches digitaldata in a memory cell latch loop formed by a pair of cross-coupledinverters in a prior art static memory cell diagram 101. A firstcomplementary inverter is constructed from a first PMOS transistor 115and a first NMOS transistor 125. A second complementary inverter isconstructed from a second PMOS transistor 120 and a second NMOStransistor 130. A pair of access devices is used to connect anddisconnect the memory cell latch loop from a bitline BL and acomplementary bitline BL. The access devices are a third NMOS transistor105 connected to the input of the first complementary inverter and afourth NMOS transistor 110 connected to the input of the secondcomplementary inverter. The access devices are enabled by a selectsignal on a wordline WL.

With reference to FIG. 1B a memory cell latch loop is represented ascross-coupled inverters 140, 145 and has two pairs of access devicesforming two access ports in a prior art dual port memory cell diagram102. Utilization of a memory array improves with simultaneous access totwo different memory locations provided by dual memory ports. A firstaccess port is formed by a first pair of NMOS transistors 110, 105connecting from the memory cell latch loop to a first bitline BL1 and afirst complementary bitline BL1 . A first wordline WL1 enables the firstpair of access devices. A second access port is formed by a second pairof NMOS transistors 165, 160 connecting from the memory cell latch loopto a second bitline BL2 and a second complementary bitline BL2 . Asecond wordline WL2 enables the second pair of access devices.

With reference to FIG. 1C a row decoder 180 selects wordlines connectedto memory cells within a memory cell array 170 in a prior art memorysystem diagram 103. A column decoder 185 selects the bitlines of thememory cells. Sense and write amplifiers 190 connect to the bitlines forreading and writing memory cells after a pair of bitlines is selected. Acontrol block 175 connects to the row decoder 180, the column decoder185, and a sense and write amplifier 190 to provide addresses andcontrol signals for read and write operations.

U.S. Pat. No. 6,005,794 entitled “Static Memory with Low Power WritePort” to Sheffield et al. describes write port circuits of a staticmemory cell that include a first conditional conduction path between afirst output of a latch and ground active if and only if both a wordlineinput and a write data true bitline input receive active signals. Thewrite port circuit includes a second conditional conduction path betweena second output of the latch and ground active if and only if both thewordline and a write data complement bitline receive active signals. Thefirst and second conditional conduction paths may be formed by a seriesconnection of the source-drain paths of two transistors. In eachconditional conduction path the gate of a first transistor receives acorresponding column signal and the gate of a second transistor isconnected to the wordline. The wordline transistors may be sharedbetween bitline transistors of a single memory cell or of memory cellsin plural contiguous adjacent columns. The memory cells may include aplurality of write ports with the write port circuit used for each portinstance. While the '794 patent uses both a pulldown stack and a pullupstack to drive the read bitline, two PMOS transistors are required ineach pullup stack replicated in every cell. The pullup stack replicationincreases an overall memory array size and complexity.

With reference to FIG. 2, a transfer curve 210 in a prior art invertertransfer characteristic diagram 200 transitions an equal potential line205 at a point with an intercept of the V_(in) axis (abscissa) andV_(out) axis (ordinate) at about $\frac{V_{DD}}{2}.$The equal potential line is a locus of points defined by an inputvoltage equaling an output voltage (V_(out)=V_(in)). The equal potentialline is therefore a line at a 45 degree angle commencing from theorigin. The transfer characteristic of the inverter is generic, having alow level input voltage V_(in) corresponding to a high level outputvoltage V_(out) and vice versa. In the case of a CMOS transistorimplementation of the inverter, the beta ratios of the pull-up deviceand the pull-down device are matched to effect the transfer curvecrossing of the equal potential line at about $\frac{V_{DD}}{2}.$

More specifically, the pull-up and pull-down device are operating intheir respective saturation regions at the operating point$V_{i\quad n} = {\frac{V_{DD}}{2}.}$In order for the transfer curve transition of the equal potential lineto occur at about $\frac{V_{DD}}{2},$the following design considerations are followed as closely as possible:With the saturation current of the p-type pull-up device being${I_{dsp} = {{- \frac{\beta_{p}}{2}}\left( {V_{i\quad n} - V_{DD} - V_{tp}} \right)^{2}}},$the saturation current of the n-type pull-down device being${I_{dsn} = {\frac{\beta_{n}}{2}\left( {V_{i\quad n} - V_{tn}} \right)^{2}}},$and with a series connection of the pull-up and pull-down devices, thenI_(dsp)=−I_(dsn). Solving for V_(in):$V_{i\quad n} = \frac{V_{DD} + V_{tp} + {V_{tn}\sqrt{\frac{\beta_{n}}{\beta_{p}}}}}{1 + \sqrt{\frac{\beta_{n}}{\beta_{p}}}}$and setting β_(n)=β_(p) and V_(tn)=−V_(tp), the result is${Vin} = {\frac{V_{DD}}{2}.}$

SUMMARY

Separate read and write ports in a memory system allow simultaneousaccess to a memory cell array in read and write operations. A singlecycle operation of a central processing unit coupled to a memory cellarray depends on a memory access capability incorporating simultaneousread and write operations. A pair of pull-down transistor stacks coupledto a memory cell latch loop allow a selected single pull-down stack ofthe pair to toggle the memory cell latch loop to a desired data contentwithout any requirement for a precharge scheme. An additional singlepull-down stack of transistors connected to a memory cell latch loopprovides a read port with low input loading and minimal likelihood ofupsetting a memory cell data content in a read operation. A senseamplifier provides a mid-supply-level precharge capability produced by afeedback device within a front-end inversion stage. The front-endinversion stage, cascaded with a second inversion stage, provides arapid read response. A memory cell of the present invention may be usedfor a register file, a specialized SRAM, or a generic SRAM.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a schematic diagram of a prior art six transistor staticmemory cell.

FIG. 1B is a schematic diagram of a prior art six transistor staticmemory cell with dual-port access.

FIG. 1C is a diagram of a prior art memory system with a memory cellarray consisting of cells such as the six transistor static memory cellof FIG. 1A.

FIG. 2 is a diagram of a transfer curve of a prior art CMOS inverter.

FIG. 3A is an exemplary schematic diagram of a static memory cell of thepresent invention.

FIG. 3B is an exemplary schematic diagram of a static memory cell withdual port read access of the present invention.

FIG. 4A is an exemplary block diagram of a sense amplifier of thepresent invention.

FIG. 4B is an equivalent circuit current flow diagram for the senseamplifier of FIG. 4A detecting a one as a data content in a readoperation of a static memory cell of FIG. 3A.

FIG. 4C is an equivalent circuit current flow diagram for the senseamplifier of FIG. 4A detecting a zero as a data content in a readoperation of a static memory cell of FIG. 3A.

FIG. 5 is a conceptual diagram of feedback behavior in a first stage ofthe sense amplifier of FIG. 4A.

FIG. 6 is an amplification characteristic diagram corresponding to asequence of inverters in the sense amplifier of FIG. 4A.

FIG. 7 is an exemplary system block diagram of the present inventionincorporating a memory array, a multiplexer, and a sense amplifier.

FIG. 8 is a logic timing diagram for a read bitline precharge and readcycle of the sense amplifier of FIG. 4A.

DETAILED DESCRIPTION AND BEST MODE

With reference to FIG. 3A, a first CMOS inverter 305 is cross-coupledwith a second CMOS inverter 310 in an exemplary schematic diagram of astatic memory cell 301. The first and second CMOS inverters 305, 310form a memory cell latch loop 333 of a static RAM cell. A first outputof the memory cell latch loop Q and a second output of the memory celllatch loop Q are formed by the outputs of the first and second CMOSinverters 305, 310 respectively. The first output of the memory celllatch loop Q connects to an output drain of a first two-transistor stack315. The second output of the memory cell latch loop Q connects to anoutput drain of a second two-transistor stack 320. The second output ofthe memory cell latch loop Q also connects to a data input of a thirdtwo-transistor stack 345. The first, second, and third two-transistorstacks 315, 320, 345 are shown, for example, as a series connection ofNMOS transistors with common source-drain diffusion and conductivechannels in series.

A wordline WL connects to a control input of each of the first andsecond two-transistor stacks 315, 320. The first and second totransistor stack 315, 320 are connected to a pair of bitlines. A firstbitline BL connects to a data input of the second two-transistor stack320. A second bitline BL connects to a data input of the firsttwo-transistor stack 315. A read bitline RBL connects to an output drainof the third two-transistor stack 345 to form a read port. A readwordline RWL connects to a first control input of the thirdtwo-transistor stack 345.

In another embodiment (not shown) the read port formed by the thirdtwo-transistor stack 345 may be used with a cell array incorporating astandard write port as in FIG. 1A. The third two-transistor stack 345,as described supra, is connected to Q and a read wordline RWL and drivesa read bitline RBL.

With reference to FIG. 3B, the second output of the memory cell latchloop Q also connects to a data input of a third and a fourthtwo-transistor stack 345, 355 in an exemplary schematic diagram of adual port static memory cell 302. The third and fourth two-transistorstacks 345, 355 are shown, for example, as a series connection of NMOStransistors with a common source-drain diffusion and conductive channelsin series.

A first read bitline RBL1 connects to an output drain of the thirdtwo-transistor stack 345 to form a first read port. A second readbitline RBL2 connects to an output drain of the fourth two-transistorstack 355 to form a second read port. A first read wordline RWL1connects to a control input of the third two-transistor stack 345. Asecond read wordline RWL2 connects to a control input of the fourthtwo-transistor stack 355.

With reference to FIG. 4A, an output of a read bitline multiplexer 405connects to an exemplary sense amplifier 440. An input to the senseamplifier 440 connects to an output drain of a pull-up device 410 and aninput of a first inverter 420. The pull-up device 410 connects to aV_(DD) level and is biased at a control input to be continually in apull-up state. The pull-up device 410 may be, for example, constructedfrom a PMOS transistor with a source node connected to V_(DD), a drainconnected to the input to the sense amplifier 440, and a control inputconnected to ground. An output of the first inverter 420 connects to aninput of a second inverter 430 and an input of a feedback device 415. Anoutput of the feedback device 415 connects to the input of the firstinverter 420. Due to the symmetrical nature of the current conductionthrough the feedback device 415 and the input of the first inverter 420,the first stage of the sense amplifier 440 is a transimpedanceamplifier. An equalization signal is connected to a control input EQ ofthe feedback device 415. An output of the second inverter 430 connectsto a data output DOUT. The equalization signal is lowered to turn offthe control input EQ to the feedback device in the exemplary embodimentin order to reduce power consumption. However, in another embodiment,the EQ may instead be tied to V_(DD) continually, for example, forfaster access times. The sense amplifier 440 will still sense while thefeedback device 415 is enabled. The transfer characteristics of thefirst inverter 420 and the second inverter 430 may be closely matchedthrough analog layout techniques to reduce offset. Analog layouttechniques to reduce the offset are well-known to ones of skill in theart.

A plurality of read bitlines (RBL1, RBL2, RBL3, . . . , RBLn) connect torespective bitline inputs of the read bitline multiplexer 405. A readaddress input RA of the read bitline multiplexer 405 receives an addressof one of the read bitlines (RBL1, RBL2, RBL3, . . . , RBLn) connectedto a memory cell to be read. A read enable input RD receives a readenable signal to control read operations. An exemplary total readbitline loading capacitance is represented by a read bitline loadingcapacitor 455 connected, for example, to a highest order bitline RBLn.

The exemplary embodiment of the present invention of FIG. 4A alsoincludes an exemplary sense amplifier 440 with an intrinsic prechargecapability. The sense amplifier 440 incorporates a feedback device 415across the first inverter 420 that causes the input to the senseamplifier 440 to seek a quiescent voltage level at about a midpointbetween V_(DD) and ground (i.e.,$\left. {V_{i\quad n} \cong \frac{V_{DD}}{2}} \right).$The sense amplifier 440 is a two-stage non-inverting buffer. A cascadingof two inverting buffer stages 420, 430 produces a high gain and a shortread access time. The short read access time allows a concurrent writeto the same memory cell array in a single clock cycle system.

With reference to FIG. 4B, a data content of a selected cell 460 is aone (“1”). The pulldown stack 345 (FIG. 3A) connected to the readbitline RBL receives a low logic level signal from the Q output of thememory cell latch loop 333. The read port formed by the pulldown stack345 is off and therefore not sinking any current through the equivalentpull down current source 465 (i.e., zero current or I=0). The pullupdevice 410 (FIG. 4A) provides a constant source current of value Irepresented by an equivalent pullup device current source 411. Thecurrent I from the equivalent pullup device current source 411 flowsinto the sense amplifier 440 input. With the feedback device 415 enabledby the input control gate connected continuously, for example, to a highvoltage level supply, the current I flows into the feedback device 415and into the output of the first inverter 420. A first equivalentcurrent source 480 indicates the current I, which entered through theoutput of the first inverter 420, flowing to ground. To provide an aidin understanding, a hypothetical (i.e., not actually a part of the senseamplifier 440 circuit) voltage potential measurement device 499 monitorsthe output of the first inverter 420 and indicates an output potentialis below the input potential of the first inverter 420 (i.e.,V_(out)<V_(in)). The difference in potential from output to input at thefirst inverter 420 is due to the equivalent current source of the pullup device 411 producing current through the (resistive) feedback device415 and causing a voltage drop from input to output (V_(in)−V_(out) ispositive) across the inverter 420. The relatively low voltage outputfrom the first inverter 420 feeds into the second inverter 430 andproduces a high level output at a DOUT node indicating the data contentof the selected cell 460 is one.

With reference to FIG. 4C, a data content of a selected cell 460 is azero (“0”). The pulldown stack 345 (FIG. 3A) connected to the readbitline RBL receives a high logic level signal from the Q output of thememory cell latch loop 333. The read port formed by the two transistorstack 345 is on and conducting a current 2I represented by theequivalent pull down current source 465. The pullup device 410 (FIG. 4A)provides a constant source current of value I represented by anequivalent pullup device current source 411. The current I from theequivalent pullup device current source 411 flows into the output of theread port pulldown stack 345 of the selected cell 460. With the feedbackdevice 415 enabled by the input control gate connected continuously, forexample, to a high voltage level supply, a current I flows out of theoutput of the first inverter 420 and into the feedback device 415. Asecond equivalent current source 485 indicates the current I enteringthe first inverter 420 at a high level supply voltage node. To providean aid in understanding, a hypothetical (i.e., not actually a part ofthe sense amplifier 440 circuit) voltage potential measurement device499 monitors the output of the first inverter 420 and indicates anoutput potential of the first inverter 420 above the input potential.The elevated output potential of the first inverter 420 is due to thecurrent sourced at the output producing current through the (resistive)feedback device 415 and causing a voltage drop from output to input(V_(in)−V_(out) is negative) across the inverter 420. The relativelyhigh voltage output from the first inverter 420 feeds into the secondinverter 430 and produces a low level output at a DOUT node indicatingthe zero data content of the selected cell 460. Therefore, the senseamplifier 440 is a transimpedance amplifier sensing the direction of thecurrent flow at an input to the sense amplifier 440.

With reference to FIG. 5, a first inverter transfer characteristic 505is cascaded with a second inverter transfer characteristic 515 in aconceptual feedback diagram 500 of feedback behavior in the first stageof the sense amplifier 440 of FIG. 4A. In the first stage of the senseamplifier 440, the output of the first inverter 420 connects to afeedback device 415. The output of the feedback device 415 connects tothe input of the first inverter 420. A graphical depiction of thefeedback characteristic is formed by a cascading of two instances of theinverter transfer characteristic 505, 515.

A generic inverter transfer curve 510 crosses an equal potential line atabout $\frac{V_{DD}}{2}$in the first inverter transfer characteristic 505. The second invertertransfer characteristic 515 is the same generic inverter transfer curve510 of the first inverter transfer characteristic 505 rotated 90°clockwise and flipped vertically. An output signal of the first inverter420 (FIG. 4A) becomes an input signal to the first inverter 420 afterpassing through the feedback device 415. Viewed graphically, the V_(out)axis of the first inverter transfer characteristic 505 is aligned withan input axis of the second inverter transfer characteristic 515 whichis labeled V_(inFB) for clarity with increasing potential depictedupward.

A change in input voltage to the sense amplifier 440 due to the pullupdevice 410 is labeled ΔV_(PU). The change in output voltage of the firststage is labeled ΔV_(out) and ranges downward along the V_(out) axis dueto the inverting nature of the first stage. The corresponding new inputto the first inverter 420 coming from the feedback device 415 isΔV_(inFB) which also ranges downward. The magnitude of ΔV_(inFB) is muchgreater than that of ΔV_(PU) due to the gain of the first stage. Thedownward ranging potential of ΔV_(inFB) in the second inverter transfercharacteristic 515 is opposite to the upward (for the axis as drawn)ranging of ΔV_(PU) and is of greater magnitude. ΔV_(inFB) thus cancelsthe tendency to increase potential at the sense amplifier 440 inputcaused by the pull up device 410. The amount of gain in the first stageis also an indicator of the strength of the precharge capability of thesense amplifier 440.

With reference to FIG. 6 a first inverter transfer characteristic 605 iscascaded with a second inverter transfer characteristic 615 in anamplification characteristic diagram 600 corresponding to the senseamplifier 440 of FIG. 4A. The first inverter transfer curve 510(repeated from FIG. 5) crosses an equal potential line at approximately$\frac{V_{DD}}{2}.$A read bitline signal range ΔV_(RBL) along the abscissa of the firstinverter transfer characteristic 605 corresponds to a large firstinverter signal output ΔV_(out1). A second inverter transfer curve 620crosses an equal potential line at approximately $\frac{V_{DD}}{2}.$The first inverter transfer curve 510 and the second inverter transfercurve 620 are matched by noting the physical layout design rules used inthe fabrication of the first and second inverters 420, 430.

The first inverter signal output ΔV_(out1) is the second inverter inputsignal ΔV_(in2) and the ordinate of the second inverter transfercharacteristic 615. An amplification characteristic of the secondinverter 430 is indicated as a sense amplifier signal output ΔV_(DOUT)along the abscissa of the second inverter transfer characteristic 615. Arelatively small magnitude of read bitline signal range ΔV_(RBL) mayproduce a variation in the sense amplifier signal output ΔV_(DOUT)spanning a nearly rail-to-rail range in potential.

With reference to FIG. 7 a memory cell array 770 connects to a senseamplifier 440 through a read bitline multiplexer 405 in an exemplarymemory system block diagram 700. A read address is provided to the readbitline multiplexer 405 at a read address input RA. The read addressprovided is used by the read bitline multiplexer 405 to select a singleone of the read bitlines (RBL1, . . . , RBLn). When a read enable signalRD_EN is received by the read bitline multiplexer 405, a single one ofthe read bitlines (RBL1, . . . , RBLn) will be selected and anelectrical path provided to the output of the read bitline multiplexer405. The output of the read bitline multiplexer 405 connects to theinput of the sense amplifier 440 (FIG. 4A). A controller 775 connects tothe memory cell array 770 to provide control signals for wordline andread wordline selection.

With reference to FIG. 8, a read address V_(RA) is received just after arising transition of a clock signal CLK in an exemplary logic timingdiagram of the memory system of FIG. 7. An equalizing precharge enablesignal EQ_EN is applied at the control signal input EQ of the senseamplifier 440 (FIG. 4A) as a standard component of a typical read cycle.The precharge enable signal EQ_EN activates the feedback device 415within the sense amplifier 440 electrically coupling the input andoutput of the first inverter 420. The sense amplifier input voltageV_(SA) _(—) _(in) is held at a high voltage level by the pullup device410 until the feedback device 415 is activated. With the feedback device415 activated, the sense amplifier input voltage V_(SA) _(—) _(in)transitions from the high voltage level to a precharge voltage potentialapproximately halfway between the supply voltage level and ground. Theprecharge transition takes place as the first inverter 420 tries tomaintain an inverter operating condition with V_(OUT)=V_(IN), asexplained supra, due to the conductive path through the feedback device415.

A read enable signal RD_EN applied to the read enable input RD of theread bitline multiplexer 405 (FIG. 4A), provides a conductive pathbetween a selected read bitline (RBL1, RBL2, . . . , RBLn) and the senseamplifier 440. With application of the read enable signal RD_EN, theread bitline voltage V_(RBL) will transition to the precharge voltagelevel produced at the input to the sense amplifier 440. The read bitlinevoltage V_(RBL), therefore, also assumes a voltage potentialapproximately halfway between the supply voltage level and ground. Asthe precharge voltage level is attained the sense amplifier 440 isprepared to read a memory cell along the memory cell column associatedwith the selected read bitline (RBL1, RBL2, . . . , RBLn). The feedbackdevice enables the sense amplifier 440 first stage sensing circuit toalso precharge a selected read bitline. A read port for one or morememory cells is accessed with a select signal applied to a read wordlineRWL (FIG. 3A). A single one of the read bitlines (RBL1, . . . , RBLn) isselected when a read address is applied to a read address input RA ofthe read bitline multiplexer 405. A single read path from a memory cellto the sense amplifier 440 is enabled by the application of the readwordline select signal RWL_SEL to the read wordline RWL and the readaddress V_(RA) applied to the read bitline multiplexer 405. The senseamplifier 440 precharges the selected one of the read bitlines (RBL1, .. . , RBLn) to a level of approximately $\frac{V_{DD}}{2}.$Only the selected read bitline (RBL1, . . . , RBLn) is precharged,thereby eliminating wasted charge on the non-selected read bitlines(RBL1, . . . , RBLn) and reducing power consumption.

The controller 775 (FIG. 7) uses the read address V_(RA) to determine aselection of a read wordline RWL (FIG. 3A). A read wordline selectsignal RWL_SEL is generated by the controller 775 and applied to thememory cell array 770. The read wordline select signal RWL_SEL isapplied to the selected read wordline RWL and is input to thetwo-transistor stack 345 read port. The read port output of the selectedmemory cell connects to the read bitline RBL. The read port will pullthe read bitline RBL low producing a low level read bitline signalV_(RBL), if a zero is stored in the selected cell or will maintain anopen or electrical tristate condition relative to the read bitline RBLwhen the contents of the selected cell is a one. A high level readbitline signal V_(RBL) is produced due to the pull up device 410 whenthe data content of the selected cell is a one.

The conductive path through the read bitline multiplexer 405 (FIG. 4A)between the sense amplifier 440 and a read bitline RBL means that thesense amplifier input voltage V_(SA) _(—) _(in) will follow the readbitline signal V_(RBL). The first inverter 420 and second invert 430connect in series within the sense amplifier 440 and produce a dataoutput signal V_(DOUT) that follows the sense amplifier input voltageV_(SA) _(—) _(in). The data output signal V_(DOUT) is produced at thedata output node DOUT after a propagation delay through the first andsecond inverters 420, 430.

The present invention has numerous additional advantages over the priorart as will be recognized by one skilled in the art. In the presentinvention the read port formed by a pulldown transistor stack connectsto the memory cell latch loop with a small single device input loading.The read port electrical connection, compared to the prior art, iscontinuous and therefore not disruptive of data contents of a memorycell due to electrical switching. The continuous connection feature ofthe present invention contrasts with access devices formed by fieldeffect transistors in a transmission gate configuration of the priorart. In the prior art, a transmission gate type connection causes asubstantial change in capacitance coupled to a memory cell duringswitching. Therefore, management of voltage potentials on bitlinesconnected by transmission gate access devices is critical in the priorart to avoid upset of the data contents of the cell. Stringent prechargeschemes result from bitline voltage management requirements in the priorart. A read port of the present invention avoids such a criticality.

Additionally, the read port electrical connection of the presentinvention, being a single device connection, is referred to as asingle-ended read port. Contrasting schemes of the prior art incorporatedifferential read ports requiring two devices to connect electricallywith the memory cell latch loop, a second read bitline, and a pulldownand a pullup stack of transistors. Conventional differential read portsrequire substantially more area for the memory cell array compared to amemory cell array constructed with single-ended read ports of thepresent invention.

A memory cell reading scheme of the present invention will select andprecharge only a single read bitline at a time. Single bitlineprecharging reduces the amount of power consumed per cycle of a readoperation significantly over prior art approaches that precharge readbitlines in bulk. The present invention also precharges selected singleread bitlines to a voltage potential about halfway between the voltagesupply level and ground. The approximate precharge voltage level of$\frac{V_{DD}}{2}$reduces the amount of time and power required to complete a prechargephase of a read operation. The amount of time and power saved contraststo prior art schemes requiring precharging to a full or nearly fullsupply voltage level. The contrast is even greater for a conventionalscheme requiring precharging to a full supply voltage level fordifferential read bitlines and for all read bitline pairs.

The sense amplifier and precharge circuitry of the present inventionminimize power expenditure in read operations by precharging only asingle read bitline to a $\frac{V_{DD}}{2}$level. The voltage feedback means for accomplishing the precharge levelis concise; requiring neither additional self-timed circuitry,additional specialized control circuitry, nor control signal routing. Aread port by the present invention utilizes single ended circuitry withlow loading of a memory cell latch loop during reading. The single endedapproach saves area and is much less likely to perturb stored datalevels during read operations compared with conventional read circuitrybased on transmission gate connectivity.

Although the present invention has been described generally in terms ofspecific embodiments, a person of skill in the art will realize thatcertain circuit elements may also be realized with alternate approaches.For instance, a buffer means, although shown as a CMOS inverter, mayalso be implemented as an operational amplifier. Even though a feedbackmeans has been depicted as an NMOS FET with a gate tied to a high-levelcontrol voltage, one skilled in the art would readily understand that aPMOS FET with a control gate tied to a low-level control voltage or ajunction field effect transistor would also accomplish the same result.While a pullup means has been presented as a PMOS FET with a gateconnected to ground potential, a person skilled in the art would readilyenvision a pull-up means fabricated from a resistor to attain a similarresult. While a writing means has been depicted as an NMOS transmissiongate, one skilled in the art would readily conceive of a PMOStransmission gate providing equivalent capability.

1. A memory system comprising: a memory cell array, the memory cellarray being a matrix of memory cells organized by rows and columns, eachof the memory cells accessible by a pair of write ports and a read port,each column of the memory cells being commonly coupled by a bitline pairand a read bitline; a row decoder, the row decoder coupled to each ofthe pairs of write ports and each of the read ports, the row decoderconfigured to receive a storage location address and couple a subset ofthe pairs of write ports and a subset of the read ports to respectivebitline pairs and respective read bitlines corresponding to the storagelocation address; a column decoder, the column decoder coupled to eachof the pairs of write ports in the memory cell array and configured toaccess a subset of the pairs of write ports in a single column of memorycells at a time in a memory cell write operation; a read bitlinemultiplexer, the read bitline multiplexer coupled to the read ports ofthe memory cell array and configured to select a subset of the readports corresponding to a single column of memory cells at a time in amemory cell read operation; a sense amplifier, the sense amplifiercoupled to the read bitline multiplexer and configured to read a datacontent from a selected memory cell, the sense amplifier furtherconfigured to precharge a single one of the read bitlines at a time in aread operation; and a control block, the control block coupled to therow decoder, the column decoder, the read bitline multiplexer, and thesense amplifier and configured to produce control signals in read andwrite operations.